AYGÜN, S. Et Al. 2017. 1.5 Bit/Stage, 12-Bit Pipeline ADC Design with Foreground Calibration. The Sixth International Conference on Advances in Computing, Electronics and Communication - ACEC 2017 , (Roma, Italy), 1-5.

AYGÜN, S., KOUHALVANDİ, L., & GÜNEŞ, E. O., (2017). 1.5 Bit/Stage, 12-Bit Pipeline ADC Design with Foreground Calibration . The Sixth International Conference on Advances in Computing, Electronics and Communication - ACEC 2017 (pp.1-5). Roma, Italy

AYGÜN, Sercan, LİDA KOUHALVANDİ, And ECE OLCAY GÜNEŞ. "1.5 Bit/Stage, 12-Bit Pipeline ADC Design with Foreground Calibration," The Sixth International Conference on Advances in Computing, Electronics and Communication - ACEC 2017, Roma, Italy, 2017

AYGÜN, Sercan Et Al. "1.5 Bit/Stage, 12-Bit Pipeline ADC Design with Foreground Calibration." The Sixth International Conference on Advances in Computing, Electronics and Communication - ACEC 2017 , Roma, Italy, pp.1-5, 2017

AYGÜN, S. KOUHALVANDİ, L. And GÜNEŞ, E. O. (2017) . "1.5 Bit/Stage, 12-Bit Pipeline ADC Design with Foreground Calibration." The Sixth International Conference on Advances in Computing, Electronics and Communication - ACEC 2017 , Roma, Italy, pp.1-5.

@conferencepaper{conferencepaper, author={Sercan AYGÜN Et Al. }, title={1.5 Bit/Stage, 12-Bit Pipeline ADC Design with Foreground Calibration}, congress name={The Sixth International Conference on Advances in Computing, Electronics and Communication - ACEC 2017}, city={Roma}, country={Italy}, year={2017}, pages={1-5} }