KIYAN, T. Et Al. 2008. Timing sensitivity analysis of logical nodes in scan design integrated circuits by pulsed diode laser stimulation. International Symposium on Testing and Failure Analysis (ISTFA) .

KIYAN, T., BRILLERT, C., & BOIT, C., (2008). Timing sensitivity analysis of logical nodes in scan design integrated circuits by pulsed diode laser stimulation . International Symposium on Testing and Failure Analysis (ISTFA)

KIYAN, Tuba, CHRISTOF BRILLERT, And CHRISTIAN BOIT. "Timing sensitivity analysis of logical nodes in scan design integrated circuits by pulsed diode laser stimulation," International Symposium on Testing and Failure Analysis (ISTFA), 2008

KIYAN, Tuba Et Al. "Timing sensitivity analysis of logical nodes in scan design integrated circuits by pulsed diode laser stimulation." International Symposium on Testing and Failure Analysis (ISTFA) , 2008

KIYAN, T. BRILLERT, C. And BOIT, C. (2008) . "Timing sensitivity analysis of logical nodes in scan design integrated circuits by pulsed diode laser stimulation." International Symposium on Testing and Failure Analysis (ISTFA) .

@conferencepaper{conferencepaper, author={Tuba KIYAN Et Al. }, title={Timing sensitivity analysis of logical nodes in scan design integrated circuits by pulsed diode laser stimulation}, congress name={International Symposium on Testing and Failure Analysis (ISTFA)}, city={}, country={}, year={2008}}