A Statically Scheduled Vector Accelerator with Explicit Data Movement Control

Sandal S., Akbas Y. C., Akturk I.

2026 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2026, Louisiana, United States Of America, 25 - 29 May 2026, pp.180-189, (Full Text)

  • Publication Type: Conference Paper / Full Text
  • Doi Number: 10.1109/ipdpsw71298.2026.00029
  • City: Louisiana
  • Country: United States Of America
  • Page Numbers: pp.180-189
  • Keywords: direct memory access, explicit control execution, static scheduling, vector processing unit
  • Yıldız Technical University Affiliated: Yes

Abstract

Dynamic scheduling can improve throughput in modern processors by tolerating variable latencies, but it also increases microarchitectural complexity and often raises energy and verification cost, while making timing behavior harder to predict. This paper presents a statically scheduled vector accelerator based on an explicit-control execution model, in which instruction issue and programmer-visible data movement are orchestrated by the compiler, and compares it against a dynamically scheduled counterpart derived from the same baseline design. The proposed design features eight streaming multiprocessors (SMs), each with an 8-lane SIMD datapath and a 128-entry vector register file (256 bits per register). We implement and evaluate two control modes on the same baseline architecture: a dynamically scheduled variant that relies on run-time arbitration, dependency tracking, and instruction re-issue to tolerate hazards and variable latencies, and a statically scheduled explicit-control variant that shifts these decisions to the compiler. By moving scheduling and data-movement orchestration out of the critical control path, the static mode reduces control complexity and improves timing determinism. Both modes are implemented in RTL via high-level synthesis and evaluated on a Xilinx Kintex UltraScale+ FPGA (KCU116) using compute-intensive benchmarks. The results demonstrate that static scheduling can reduce cycle count by up to 13.5% (on average of 6.8%) compared to dynamic control, indicating that compile-time control can be a practical and efficient alternative.