Transistor Size Estimation Based on Propagation Delay in CMOS Digital Circuits Using Neural Networks | AVESİS

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Transistor Size Estimation Based on Propagation Delay in CMOS Digital Circuits Using Neural Networks

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Ünal C., Kahraman N., Yıldırım T.

Proc. of INISTA 2005 International Symposium on Innovations in Intelligent SysTems and Applications, İstanbul, Turkey, 15 - 18 June 2005, pp.1-5

Publication Type: Conference Paper / Full Text
City: İstanbul
Country: Turkey
Page Numbers: pp.1-5
Yıldız Technical University Affiliated: Yes