Analog multiplication circuits are very important blocks widely used in analog signal processing applications. In analog multiplication circuits, low power consumption is expected with wide bandwidth, low nonlinearity and high input range according to the supply voltage. In this work, folded Gilbert cell structure was resized using dynamic threshold MOS (DTMOS) transistors. The proposed circuit is laid out with 491.4 μm2 chip area. Post layout simulations show that the proposed circuit has high bandwidth (1.2 GHz), low supply voltage (0.2 V ), and low power consumption (44.6 μW ). In addition, the proposed circuit is examined for temperature variation, total harmonic distortion, intermodulation products and Monte Carlo analysis of the dimensioning of the circuit. The post layout results show that the proposed circuit has promising performance against its counterparts in the literature.