Akademik Veri Yönetim Sistemi
Electronics (Switzerland), cilt.15, sa.4, 2026 (SCI-Expanded, Scopus)
NAND flash memory reliability is increasingly challenged by rising data density and frequent program/erase cycles. While Error Correction Codes (ECC) are standard, the simultaneous use of ECC-embedded NAND and ECC-capable host systems is generally avoided due to the risk of unpredictable behavior and file system corruption. Existing studies on the use of dual ECC primarily focus on switching between different ECC structures or adaptive decoding based on error rates and data characteristics. In contrast, this paper introduces a novel driver-level coordination framework that enables the concurrent and integrated operation of two independent ECC mechanisms. By managing the interaction within the Memory Technology Device (MTD) layer, our approach enables the simultaneous utilization of internal NAND ECC and host-side ECC—a combination traditionally considered incompatible. Our approach improves overall system reliability and relaxes product-matching restrictions. Although the solution introduces a minor latency penalty, it is highly effective for applications where data integrity is the primary concern. Experimental results demonstrate that our solution prevents data corruption and extends the lifetime of NAND flash memory.