Dolunay: Architectural Support for Independent Thread Scheduling in a RISC-V SIMT Accelerator
WiPiEC Journal - Works in Progress in Embedded Computing Journal, vol.12, no.2, pp.17-24, 2026 (Peer-Reviewed Journal)
- Publication Type: Article / Article
- Volume: 12 Issue: 2
- Publication Date: 2026
- Doi Number: 10.64552/wipiec.v12i2.137
- Journal Name: WiPiEC Journal - Works in Progress in Embedded Computing Journal
- Journal Indexes: Index Copernicus
- Page Numbers: pp.17-24
- Open Archive Collection: AVESIS Open Access Collection
- Yıldız Technical University Affiliated: Yes
Abstract
Single-Instruction Multiple-Thread (SIMT) architectures have revolutionized data-parallel computing by providing a high-throughput abstraction that simplifies vector management. However, traditional stack-based SIMT models do not support intra-warp synchronization primitives such as mutexes and spin-locks. This work introduces Dolunay, a RISC-V-based Independent Thread Scheduling (ITS) SIMT accelerator. By only adding three custom instructions, Dolunay employs a cooperative multitasking model and explicit synchronization barriers at the hardware-level, and provides the forward-progress guarantees necessary to implement starvation-free algorithms. We evaluate Dolunay on the Cmod A7-35T FPGA module and demonstrate its ability to correctly execute kernels that deadlock on traditional stack-based architectures while still achieving parallel execution for conventional compute-heavy kernels.