Pareto Optimal Characterization of a Microwave Transistor

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Güneş F., Uluslu A., Mahouti P.

IEEE ACCESS, vol.8, pp.47900-47913, 2020 (SCI-Expanded) identifier identifier

  • Publication Type: Article / Article
  • Volume: 8
  • Publication Date: 2020
  • Doi Number: 10.1109/access.2020.2978415
  • Journal Name: IEEE ACCESS
  • Journal Indexes: Science Citation Index Expanded (SCI-EXPANDED), Scopus, Compendex, INSPEC, Directory of Open Access Journals
  • Page Numbers: pp.47900-47913
  • Keywords: Pareto optimization, Transistors, Microwave transistors, Genetic algorithms, Performance evaluation, Microwave amplifiers, Non-dominated sorting genetic algorithm, Pareto optimal solutions, optimization, impedance mismatching, transducer gain, noise figure, PERFORMANCE CHARACTERIZATION, MULTIOBJECTIVE OPTIMIZATION, GENETIC ALGORITHM, NOISE, SIGNAL, DESIGN, PARAMETERS, POWER, AMPLIFIER, MODEL
  • Yıldız Technical University Affiliated: Yes


Herein, noise, gain and port mismatchings of a microwave small-signal transistor are expressed as all the set of acceptable Pareto optimal solutions and trade-off relations within the device operation (VDS, IDS, f) domain without any need of expert knowledge of microwave device. In this multi-objective optimization problem, non-dominated sorting genetic algorithm (NSGA) -III is applied to an ultra-low noise amplier (LNA) transistor NE3511S02 (HJ-FET) where the noise Freq >= Fmin and output mismatching Voutreq >= 1 are preferred as the reference points, while the input mismatching Vinopt >= 1 and gain GTmax are optimized with respect to source ZS and load ZL within the unconditionally stable working area. Thus, diverse set of the Pareto optimal (the required noise Freq, the optimum input Vinopt, the required output Voutreq, the maximum transducer gain GTmax) quadruples are resulted from a fast search of the solution space. Furthermore, the optimum bias condition (VDS, IDS) and sensitivities of the terminations to fabrication tolerances are also determined using the cost analysis in the operation domain for the required Pmax, IDSmax and performance quadruple. Finally, this work is expected to enable a designer to provide the feasible design target space (FDTS) consisting of all trade-off relations among all the transistor's performance ingredients to be used in the challenging LNA designs.