Technology independent circuit sizing for standard cell based design using neural networks


DIGITAL SIGNAL PROCESSING, vol.19, no.4, pp.708-714, 2009 (SCI-Expanded) identifier identifier

  • Publication Type: Article / Article
  • Volume: 19 Issue: 4
  • Publication Date: 2009
  • Doi Number: 10.1016/j.dsp.2008.11.009
  • Journal Indexes: Science Citation Index Expanded (SCI-EXPANDED), Scopus
  • Page Numbers: pp.708-714
  • Yıldız Technical University Affiliated: Yes


This paper presents a neural network (NN) approach for modeling the time characteristics of fundamental gates of digital integrated circuits that include inverter, NAND, NOR, and XOR gates. The modeling approach presented here is technology independent, fast, and accurate, which makes it suitable for circuit simulators. Firstly transient simulations were done in order to obtain delay times for different transistor sizes and different load capacitances using AMIS 1.5 mu m, TSMC 0.25 mu m and TSMC 0.18 mu m technology parameters with HSPICE. These delay time results constitute the inputs of NN while the outputs are transistor sizes. Then, two neural network structures, multilayer perceptron (MLP) and general regression neural network (GRNN), were compared to estimate the transistor sizes. MLP achieved 91 acceptable results through 120 test data where GRNN had 77. The important thing is that the NN is able to generalize the input-output mapping and estimates the outputs for new data which were not applied to the NN for training before. As a conclusion, fundamental gates used for standard cell based VLSI design can be sized for desired delay times using neural networks without knowing SPICE technology parameters. (c) 2008 Elsevier Inc. All rights reserved.