This paper presents analysis and design of a two-stage CMOS operational amplifier (opamp) which consists of rail-to-rail gain-boosted folded cascode amplifier in order to enhance speed and DC gain from 68 dB to 123 dB in the input stage and also rail-to-rail class AB in output stage for maximizing signal-to-noise (SNR) ratio. It is simulated in 350nm CMOS technology in Cadence Spectre Circuit Simulator with 3.3 V power supply. This opamp achieves high DC gain of 156 dB and a phase margin of 69 degrees with a 5 pF load and minimum settling time of 22.3 ns while consuming power less than 7 mW along with a PSRR more than 90 dB. The overall result is the increased gain, reduced power consumption and fast high speed settling time. Therefore, the proposed opamp can be utilized in high speed and high-resolution Analog-to-Digital converters (ADCs) like pipeline ADC.