Design Optimization of Microstrip Matching Circuits Using a Honey Bee Mating Algorithm Subject to the Transistor's Potential Performance


Mahouti P. , Demirel S. , GÜNEŞ F.

Progress In Electromagnetics Research Symposium, Stockholm, İsveç, 12 - 15 Ağustos 2013, ss.1890-1893

  • Basıldığı Şehir: Stockholm
  • Basıldığı Ülke: İsveç
  • Sayfa Sayısı: ss.1890-1893

Özet

In this work, the same Honey Bee Mating Optimization as in [1], this time is applied to design of the input and output microstrip matching circuits to provide the source Z(S) and load Z(L) terminations ensuring the selected performance quadrate to the transistor, respectively for the desired performance triplets (V-in, F(f), G(T)) [1, 2]. In this implementation, the populations of the Queen Candidates and Drones are defined in terms of the widths (W) over right arrow and lengths (l) over right arrow of the input and output microstrip matching circuits to determine the fitness values or estrogen values of the bees. Among the female bees probabilistically mating with the drones, the one with the fittest gens or estrogen level will be chosen as the Queen bee, in the other words, the best solution for optimization problem. On the other hand, the multi-objective design optimization procedure of the amplifier is reduced into the single objective design procedures of the input/output matching circuits using Darlington realizations of the quadrate Z(S), Z(L), terminations. It can be concluded that in this work, all the constituents of the HBMO design optimization are defined rigorously and at the output, all the microstrip lengths and widths of the input and output matching circuits are obtained to be printed on a selected dielectric substrate. Finally as a work example the design of a typically ultra-wide band low noise amplifier with NE3512502 is presented on a substrate of Rogers 4350 (epsilon(r) = 3.48, h = 1.524 mm, tan delta = 0.003, t = 0.001 mm) within 2-5 GHz satisfying (V-in = 1.5, F = F-min(f), G(T) = 10 dB) triplet using the T type of microstrip matching circuit and verified using the circuit simulator AWR.