Performance Analysis of Fault Current Limiting Methods on IEEE 9-Bus System

Kucukaydin B., ARIKAN O.

11th International Conference on Electrical and Electronics Engineering (ELECO), Bursa, Turkey, 28 - 30 November 2019, pp.131-135 identifier identifier

  • Publication Type: Conference Paper / Full Text
  • Volume:
  • Doi Number: 10.23919/eleco47770.2019.8990460
  • City: Bursa
  • Country: Turkey
  • Page Numbers: pp.131-135
  • Yıldız Technical University Affiliated: Yes


The fault current levels gradually increase with becoming widespread of distributed generation units, expansion of power systems, increased current levels, and power demand. High fault currents can cause damage to the power system components or shorten their life. This can bring about serious economic costs and affect the reliability of the system. In this study, three different fault current limiting methods such as current limiting series reactor, high impedance transformer and controlled series reactor (solid-state) fault current limiter that is applied in the IEEE 9-bus system are analyzed for three-phase fault and their effects to the system are discussed for normal operating conditions. The power system and current limiters are modeled in PSCAD/EMTDC.