Research Information System
AEU - International Journal of Electronics and Communications, vol.214, 2026 (SCI-Expanded, Scopus)
Memristor-based in-memory computing has been extensively explored to reduce data movement overhead; however, conventional stateful logic implementations of arithmetic operations often require many sequential steps and repeated read/write operations, leading to increased latency. This work presents a majority-based in-memory full adder architecture in which a dedicated MAJ structure is mapped onto a memristive crossbar array. Using a 5T1R-based crossbar configuration, the proposed design realizes a 1-bit full adder in only three computation steps. By formulating arithmetic operations using majority logic and implementing them within a MAJ-based stateful logic framework, the complete 1-bit addition is executed in a single cycle while preserving input states. The architecture is validated through Spice simulations using a realistic memristor model, demonstrating correct functionality along with reduced computation latency and energy consumption, and confirming its suitability for fast single-cycle in-memory arithmetic.