Analog circuit sizing via swarm intelligence

Vural R. , YILDIRIM T.

AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, vol.66, no.9, pp.732-740, 2012 (Journal Indexed in SCI) identifier identifier

  • Publication Type: Article / Article
  • Volume: 66 Issue: 9
  • Publication Date: 2012
  • Doi Number: 10.1016/j.aeue.2012.01.003
  • Page Numbers: pp.732-740
  • Keywords: CMOS analog integrated circuit sizing, Particle swarm optimization, Circuit design automation, Area oriented optimization, PARTICLE SWARM, DESIGN, CMOS, OPTIMIZATION, FRAMEWORK, TOOL


Together with the increase in electronic circuit complexity, the design and optimization processes have to be automated with high accuracy. Predicting and improving the design quality in terms of performance, robustness and cost is the central concern of electronic design automation. Generally, optimization is a very difficult and time consuming task including many conflicting criteria and a wide range of design parameters. Particle swarm optimization (PSO) was introduced as an efficient method for exploring the search space and handling constrained optimization problems. In this work, PSO has been utilized for accommodating required functionalities and performance specifications considering optimal sizing of analog integrated circuits with high optimization ability in short computational time. PSO based design results are verified with SPICE simulations and compared to previous studies. (C) 2012 Elsevier GmbH. All rights reserved.