1.5 Bit/Stage, 12-Bit Pipeline ADC Design with Foreground Calibration

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Aygün S., Kouhalvandi L., Güneş E. O.

International Journal of Advancements in Electronics & Electrical Engineering, vol.7, no.1, pp.164-168, 2018 (Conference Book)


In this paper, 12-Bit pipeline ADC is to be designed together with caring non-idealities. Pipeline issue in modern computers is quite advantageous for performance. Such structure can be constructed in analog-to-digital converters to make the performance faster. By considering the non-ideal cases for the design, more realistic outputs are expected. There are several non-ideal effects that lower the ADC performance such as gain error and capacitor mismatches. By using calibration techniques like background or foreground calibration, non-ideal effects can be reduced. In this paper, foreground calibration technique is applied and tabloid results are presented at the end. Modelling of the pipeline ADC is constructed on Matlab Simulink environment.