Timing sensitivity analysis of logical nodes in scan design integrated circuits by pulsed diode laser stimulation

KIYAN T., BRILLERT C., BOIT C.

International Symposium on Testing and Failure Analysis (ISTFA), 01 Kasım 2008

  • Yayın Türü: Bildiri / Tam Metin Bildiri
  • Yıldız Teknik Üniversitesi Adresli: Evet